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<title>MOVLPS—Move Low Packed Single-Precision Floating-Point Values </title></head>
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<h1>MOVLPS—Move Low Packed Single-Precision Floating-Point Values</h1>
<table>
<tr>
<th>Opcode/Instruction</th>
<th>Op / En</th>
<th>64/32 bit Mode Support</th>
<th>CPUID Feature Flag</th>
<th>Description</th></tr>
<tr>
<td>
<p>0F 12 /r</p>
<p>MOVLPS xmm1, m64</p></td>
<td>RM</td>
<td>V/V</td>
<td>SSE</td>
<td>Move two packed single-precision floating-point values from m64 to low quadword of xmm1.</td></tr>
<tr>
<td>
<p>VEX.NDS.128.0F.WIG 12 /r</p>
<p>VMOVLPS xmm2, xmm1, m64</p></td>
<td>RVM</td>
<td>V/V</td>
<td>AVX</td>
<td>Merge two packed single-precision floating-point values from m64 and the high quadword of xmm1.</td></tr>
<tr>
<td>
<p>EVEX.NDS.128.0F.W0 12 /r</p>
<p>VMOVLPS xmm2, xmm1, m64</p></td>
<td>T2</td>
<td>V/V</td>
<td>AVX512F</td>
<td>Merge two packed single-precision floating-point values from m64 and the high quadword of xmm1.</td></tr>
<tr>
<td>
<p>0F 13/r</p>
<p>MOVLPS m64, xmm1</p></td>
<td>MR</td>
<td>V/V</td>
<td>SSE</td>
<td>Move two packed single-precision floating-point values from low quadword of xmm1 to m64.</td></tr>
<tr>
<td>
<p>VEX.128.0F.WIG 13/r</p>
<p>VMOVLPS m64, xmm1</p></td>
<td>MR</td>
<td>V/V</td>
<td>AVX</td>
<td>Move two packed single-precision floating-point values from low quadword of xmm1 to m64.</td></tr>
<tr>
<td>
<p>EVEX.128.0F.W0 13/r</p>
<p>VMOVLPS m64, xmm1</p></td>
<td>T2-MR</td>
<td>V/V</td>
<td>AVX512F</td>
<td>Move two packed single-precision floating-point values from low quadword of xmm1 to m64.</td></tr></table>
<h3>Instruction Operand Encoding</h3>
<table>
<tr>
<td>Op/En</td>
<td>Operand 1</td>
<td>Operand 2</td>
<td>Operand 3</td>
<td>Operand 4</td></tr>
<tr>
<td>RM</td>
<td>ModRM:reg (r, w)</td>
<td>ModRM:r/m (r)</td>
<td>NA</td>
<td>NA</td></tr>
<tr>
<td>RVM</td>
<td>ModRM:reg (w)</td>
<td>VEX.vvvv</td>
<td>ModRM:r/m (r)</td>
<td>NA</td></tr>
<tr>
<td>MR</td>
<td>ModRM:r/m (w)</td>
<td>ModRM:reg (r)</td>
<td>NA</td>
<td>NA</td></tr>
<tr>
<td>T2</td>
<td>ModRM:reg (w)</td>
<td>EVEX.vvvv</td>
<td>ModRM:r/m (r)</td>
<td>NA</td></tr>
<tr>
<td>T2-MR</td>
<td>ModRM:r/m (w)</td>
<td>ModRM:reg (r)</td>
<td>NA</td>
<td>NA</td></tr></table>
<p><strong>Description</strong></p>
<p>This instruction cannot be used for register to register or memory to memory moves.</p>
<p><strong>128-bit Legacy SSE load:</strong></p>
<p>Moves two packed single-precision floating-point values from the source 64-bit memory operand and stores them in the low 64-bits of the destination XMM register. The upper 64bits of the XMM register are preserved. Bits (MAX_VL-1:128) of the corresponding destination register are preserved.</p>
<p><strong>VEX.128 &amp; EVEX encoded load:</strong></p>
<p>Loads two packed single-precision floating-point values from the source 64-bit memory operand (the third operand), merges them with the upper 64-bits of the first source operand (the second operand), and stores them in the low 128-bits of the destination register (the first operand). Bits (MAX_VL-1:128) of the corresponding desti-nation register are zeroed.</p>
<p><strong>128-bit store:</strong></p>
<p>Loads two packed single-precision floating-point values from the low 64-bits of the XMM register source (second operand) to the 64-bit memory location (first operand).</p>
<p>Note: VMOVLPS (store) (VEX.128.0F 13 /r) is legal and has the same behavior as the existing 0F 13 store. For VMOVLPS (store) VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instruction will #UD.</p>
<p>If VMOVLPS is encoded with VEX.L or EVEX.L’L= 1, an attempt to execute the instruction encoded with VEX.L or EVEX.L’L= 1 will cause an #UD exception.</p>
<p><strong>Operation</strong></p>
<p><strong>MOVLPS (128-bit Legacy SSE load)</strong></p>
<p>DEST[63:0] (cid:197) SRC[63:0]</p>
<p>DEST[MAX_VL-1:64] (Unmodified)</p>
<p><strong>VMOVLPS (VEX.128 &amp; EVEX encoded load)</strong></p>
<p>DEST[63:0] (cid:197) SRC2[63:0]</p>
<p>DEST[127:64] (cid:197) SRC1[127:64]</p>
<p>DEST[MAX_VL-1:128] (cid:197) 0</p>
<p><strong>VMOVLPS (store)</strong></p>
<p>DEST[63:0] (cid:197) SRC[63:0]</p>
<p><strong>Intel C/C++ Compiler Intrinsic Equivalent</strong></p>
<p>MOVLPS __m128 _mm_loadl_pi ( __m128 a, __m64 *p)</p>
<p>MOVLPS void _mm_storel_pi (__m64 *p, __m128 a)</p>
<p><strong>SIMD Floating-Point Exceptions</strong></p>
<p>None</p>
<p><strong>Other Exceptions</strong></p>
<p>Non-EVEX-encoded instruction, see Exceptions Type 5; additionally</p>
<table>
<tr>
<td>#UD</td>
<td>
<p>If VEX.L = 1.</p>
<p>EVEX-encoded instruction, see Exceptions Type E9NF.</p></td></tr></table></body></html>